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?2002 integrated device technology, inc. dsc-5654/1 1

true dual-ported memory cells which allow simultaneous access of the same memory location high-speed clock to data access ? commercial:7.5/9/12ns (max.) ? industrial: 9ns (max.) low-power operation ? idt70t9169/59l active: 225mw (typ.) standby: 1.5mw (typ.) flow-through or pipelined output mode on either port via the ft /pipe pins counter enable and reset features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 4.0ns setup to clock and 0.5ns hold on all control, data, and address inputs ? data input, address, and control registers ? fast 7.5ns clock to data out in the pipelined output mode ? self-timed write allows fast cycle time ? 12ns cycle time, 83mhz operation in pipelined output mode lvttl- compatible, single 2.5v (100mv) power supply industrial temperature range (?40c to +85c) is available for 66mhz available in a 100-pin thin quad flatpack (tqfp) and 100- pin fine pitch ball grid array (fpbga) packages. high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram idt70t9169/59l 0 1 0/1 1 0/1 0 r/ w r oe r ce 0r ce 1r ft /pipe r i/o control memory array counter/ address reg. i/o control 5654 drw 01 a 13r (1) a 0r clk r ads r cnten r cntrst r a 0l clk l ads l a 13l (1) cnten l cntrst l counter/ address reg. r/ w l ce 0l oe l ce 1l i/o 0l -i/o 8l i/o 0r -i/o 8r 1 0/1 0 0 1 0/1 ft /pipe l preliminary note: 1. a 13 is a nc for idt70t9159.
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 2 preliminary index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100999897 9695 949392 9190 8988 8786 8584 838281 8079 7877 76 100-pin tqfp top view (6) nc nc a 7l a 8l a 9l a 10l a 11l a 12l a 13l (1) nc nc nc v dd nc nc nc ce 0l nc ce 1l cntrst l r/ w l oe l ft /pipe l nc nc 5654 drw 02 nc nc a 7r a 8r a 9r a 10r a 11r a 12r a 13r (1) nc nc vss nc nc nc nc oe r ft /pipe r vss nc nc ce 0r ce 1r cntrst r r/ w r n c n c a 6 l a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l c n t e n l c l k l a d s l v s s v s s a d s r c l k r c n t e n r a 0 r a 2 r a 3 r a 4 r a 5 r a 6 r n c v s s i / o 8 l v d d i / o 7 l i / o 6 l i / o 5 l i / o 4 l i / o 3 l i / o 2 l v s s i / o 1 l v s s i / o 0 r i / o 1 r i / o 2 r i / o 0 l i / o 4 r i / o 5 r i / o 6 r i / o 7 r i / o 8 r n c n c a 1 r i / o 3 r . v d d 70t9169/59pf pn100-1 (5) 06/21/02
the idt70t9169/59 is a high-speed 16/8k x 9 bit synchronous dual- port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt70t9169/59 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 225mw of power. notes: 1. a 13 is a nc for idt70t9159. 2. all v dd pins must be connected to power supply. 3. all v ss pins must be connected to ground supply. 4. package body is approximately 14mm x 14mm x 1.4mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking.

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6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 3 preliminary c10 i/o 3r d8 i/o 8r c8 pl/ ft r a9 v ss d9 i/o 5r c9 i/o 7r b9 nc d10 i/o 1r c7 ce 1r b8 oe r a8 r/ w r a10 nc d7 cntrst r b7 nc a7 nc b6 nc c6 ce 0r d6 a 13r (1) a5 v ss b5 nc c5 nc d5 a 11r a4 nc b4 a 10r c4 a 7r d4 a 2r a3 a 12r b3 a 8r c3 nc d3 a 1r d2 clk r c2 nc b2 a 5r a2 a 9r a1 a 6r b1 a 4r c1 a 3r d1 a 0r e1 v ss e2 ads r e3 cnten r e4 a 1l f1 v ss f2 clk l f3 a 0l f4 a 3l g1 cnten l g2 nc g3 a 5l g4 a 12l h1 a 2l h2 a 4l h3 a 9l h4 a 13l (1) j1 nc j2 a 7l j3 a 10l j4 nc k1 a 6l k2 a 8l k3 a 11l k4 nc a6 v ss b10 i/o 6r e5 ads l e6 v ss e7 i/o 4r e8 i/o 2r e9 i/o 0r e10 v dd f5 v dd f6 v ss f8 i/o 2l f9 i/o 1l f10 i/o 0l g5 nc g6 r/ w l g7 nc g8 i/o 4l g9 v ss g10 i/o 3l h5 nc h6 ce 1l h7 nc h8 i/o 7l h9 i/o 6l h10 i/o 5l j5 nc j6 nc j7 oe l j8 v ss j9 v ss j10 i/o 8l k5 v dd k6 v dd k7 ce 0l k8 cntrst l k9 pl/ ft l k10 nc f7 v dd 5654 drw 03 , 06/21/02 70t9169/59bf bf100 (5) 100-pin fpbga top view (6) notes: 1. a 13 is a nc for idt70t9159. 2. all v dd pins must be connected to power supply. 3. all v ss pins must be connected to ground supply. 4. package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking.

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6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 4 preliminary notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , cntrst = x. 3. oe is an asynchronous input signal. % &%'()*+,-
+.
'
" oe clk ce 0 ce 1 r/ w i/o 0-8 mode x h x x high-z deselected ? power down x x l x high-z deselected ? power down x lhl data in write l lhhdata out read h x l h x high-z outputs disabled 5654 tbl 02
/ left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 13 l (1) a 0r - a 13r (1) address i/o 0l - i/o 8l i/o 0r - i/o 8r data input/output clk l clk r clo ck ads l ads r address strobe cnten l cnten r counter enable cntrst l cntrst r co unter res et ft /pipe l ft /pipe r flow-through/pipeline v dd power (2.5v) v ss ground (0v) 56 54 tbl 01 note: 1. a 13 is a nc for idt70t9159.
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 5 preliminary *
++0
%
+1 23 *
++0

+
4' 56 *
"
" % 4 789:7$5; < " grade ambient temperature (1 ) gnd v dd commercial 0 o c to +70 o c0v2.5v + 100mv industrial -40 o c to +85 o c0v2.5v + 100mv 5654 tbl 04 symbol parameter min. typ. max. unit v dd supp ly vo ltage 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high voltage 1.7 ____ v dd +0.3v (2) v v il input low voltage -0.3 (1) ____ 0.7 v 56 54 tbl 05 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 9 pf c out (3 ) output capacitance v out = 3dv 10 pf 5654 tbl 07 symbol rating commercial & industrial unit v te r m (2 ) terminal voltage with respect to gnd -0.5 to +3.6 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 5654 tbl 06 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ce 0 and oe = v il ; ce 1 and r/ w = v ih . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and cntrst are independent of all other signals including ce 0 and ce 1 . 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other signals including ce 0 and ce 1 . % &%'(()4++

" external address previous internal address internal address used clk ads cnten cntrst i/o (3) mode an x an l (4) xhd i/o (n) external address used xanan + 1 h l (5) hd i/o (n+1) counter enabled ? internal address generation x an + 1 an + 1 hh hd i/o (n+1) external address blocked ? counter disab led (an + 1 reused) xxa 0 xx l (4) d i/o (0) counter reset to address 0 5654 tbl 0 3 notes: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v il > -1.5v for pulse width less than 10 ns. 2. v term must not exceed v dd +0.3v. notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v dd + 0.3v.
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 6 preliminary . & 0=&0
%
+1 23*
" 3 7$93>3" 70t9169/59l7 com'l only 70t9169/59l9 com'l & ind 70t9169/59l12 com'l only symbol parameter test condition version typ. (4 ) max. typ. (4 ) max. typ. (4 ) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1 ) com'l l 80 200 75 175 70 150 ma ind l ____ ____ 75 220 ____ ____ i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1 ) com'l l 20 60 20 50 20 40 ma ind l ____ ____ 20 70 ____ ____ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5 ) active port outputs disabled, f=f max (1 ) com'l l 50 115 47 100 45 85 ma ind l ____ ____ 47 190 ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2 ) com'l l 0.1 3.0 0.1 3.0 0.1 3.0 ma ind l ____ ____ 0.1 3.0 ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5 ) v in > v dd - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1 ) com'l l 50 115 47 100 45 85 ma ind l ____ ____ 47 190 ____ ____ 5654 tbl 09 . & 0=&0
% 1 23*
3 7$93>3" note: 1. at vcc < 2.0v input leakages are undefined. symbol parameter test conditions 70t9169/59l unit min. max. |i li | input leakage current (1 ) v dd = 2.6v, v in = 0v t o v dd ___ 5a |i lo | output leakage current ce = v ih or ce 1 = v il , v out = 0v t o v dd ___ 5a v ol output low voltage i ol = +2ma ___ 0.4 v v oh output high voltage i oh = -2ma 2.0 ___ v 5654 tb l 0 8 notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 2.5v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 2.5v, t a = 25 c for typ, and are not production tested. i dd dc (f=0) = 75ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v dd - 0.2v ce x > v dd - 0.2v means ce 0x > v dd - 0.2v or ce 1x < 0.2v "x" represents "l" for left port or "r" for right port.
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 7 preliminary 4%
+
figure 2. typical output derating (lumped capacitive load). input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 2.5v 2ns max. 1.25v 1.25v figures 1 and 2 5654 tbl 10 ? capacitance (pf) from ac test load ? tcd (typical, ns) 5654 drw 06 1.25v 50 ? 50 ? 5654 drw 04 10pf / 5pf* (tester) data out , * (for t cklz , t ckhz , t olz , and t ohz ). figure 1. ac output test load.
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 8 preliminary notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guarant eed by device characteriza- tion, but is not production tested. 2. the pipelined output parameters (t cyc2 , t cd2 ) to either the left or right ports when ft /pipe = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port . 3. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ), ft /pipe r and ft /pipe l. 4. & 0=&0
% *
*+
+- 2%
" " 3 7$93>3% 4 7:8?:" 70t9169/59l7 com'l only 70t9169/59l9 com'l & ind 70t9169/59l12 com'l only symbol parameter min. max. min. max. min. max. unit t cyc1 clock cycle time (flow-through) (2 ) 22 ____ 25 ____ 30 ____ ns t cyc2 clock cycle time (pipelined) (2 ) 12 ____ 15 ____ 20 ____ ns t ch1 clock high time (flow-through) (2 ) 7.5 ____ 12 ____ 12 ____ ns t cl 1 clock low time (flow-through) (2 ) 7.5 ____ 12 ____ 12 ____ ns t ch2 clock high time (pipelined) (2 ) 5 ____ 6 ____ 8 ____ ns t cl 2 clock low time (pipelined) (2 ) 5 ____ 6 ____ 8 ____ ns t r clock rise time ____ 3 ____ 3 ____ 3ns t f clock fall time ____ 3 ____ 3 ____ 3ns t sa address setup time 4 ____ 4 ____ 4 ____ ns t ha address hold time 0 ____ 1 ____ 1 ____ ns t sc chip enable setup time 4 ____ 4 ____ 4 ____ ns t hc chip enable hold time 0 ____ 1 ____ 1 ____ ns t sb byte enable setup time 4 ____ 4 ____ 4 ____ ns t hb byte enable hold time 0 ____ 1 ____ 1 ____ ns t sw r/ w setup time 4 ____ 4 ____ 4 ____ ns t hw r/ w hold time 0 ____ 1 ____ 1 ____ ns t sd input data setup time 4 ____ 4 ____ 4 ____ ns t hd input data hold time 0 ____ 1 ____ 1 ____ ns t sad ads setup time 4 ____ 4 ____ 4 ____ ns t ha d ads hold time 0 ____ 1 ____ 1 ____ ns t scn cnten setup time 4 ____ 4 ____ 4 ____ ns t hcn cnten hold time 0 ____ 1 ____ 1 ____ ns t srst cntrst setup time 4 ____ 4 ____ 4 ____ ns t hrst cntrst hold time 0 ____ 1 ____ 1 ____ ns t oe output enable to data valid ____ 7.5 ____ 9 ____ 12 ns t olz output enable to output low-z (1 ) 2 ____ 2 ____ 2 ____ ns t ohz output enable to output high-z (1 ) 17 17 17ns t cd1 clock to data valid (flow-through) (2 ) ____ 18 ____ 20 ____ 25 ns t cd2 clock to data valid (pipelined) (2 ) ____ 7.5 ____ 9 ____ 12 ns t dc data output hold after clock high 2 ____ 2 ____ 2 ____ ns t ckhz clock high to output high-z (1 ) 292929ns t cklz clock high to output low-z (1 ) 2 ____ 2 ____ 2 ____ ns port-to-port delay t cwdd write port clock high to read data delay ____ 28 ____ 35 ____ 40 ns t ccs clock-to-clock setup time ____ 10 ____ 15 ____ 15 ns 5654 tbl 11
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 9 preliminary %
-=*+2@a%& &0 ft ,(. bcb 73 ( " d" %
-=*+2
+0
ft ,(. bcb 73 (; " d" notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ads = v il , cnten and cntrst = v ih . 4. the output is disabled (high-impedance state) by ce 0 = v ih or ce 1 = v il following the next rising edge of the clock. refer to truth table 1. 5. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 6. "x" here denotes left or right port. the diagram is with respect to that port. an an + 1 an + 2 an + 3 r/ w address data out oe t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5654 drw 07 (1) (1) (1) (1) (2) t sw t hw t sa t ha t dc t dc (5) t cyc1 t ch1 t cl1 ce 0 clk t sc t hc ce 1 t sc t hc an an + 1 an + 2 an + 3 r/ w address data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5654 drw 08 (1) (1) (1) (2) t sw t hw t sa t ha t dc (5) (1 latency) (6) t cyc2 t ch2 t cl2 ce 0 clk ce 1 (4) t sc t hc t sc t hc
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 10 preliminary %
-=- @ &aa@a%& &*+ !9?" notes: 1. b1 represents bank #1; b2 represents bank #2. each bank consists of one idt70t9169/59 for this waveform, and are setup for de pth expansion in this example. address (b1) = address (b2) in this situation. 2. oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and cntrst = v ih . 3. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 4. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 5. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 6. if t ccs < maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data from right port read is not valid until t ccs + t cd1 . t cwdd does not apply in this case. 7. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite fro m port "a". %
-=
1
+*+ " t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 5654 drw 09 q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 (3) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz (3) (3) t sc t hc (3) t ckhz (3) t cklz (3) t cd2 a 6 a 6 t dc t sc t hc t sc t hc data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cwdd t cd1 t dc data out "b" 5654 drw 10 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t ccs t dc t sa t sw t ha (6) (6)
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 11 preliminary %
-=
+*+aa- aa*+ oe 73 ( " " %
-=

+*+aa- aa*+ oe
+" " notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 5654 drw 11 qn qn + 3 data out t cd2 t ckhz t cklz t cd2 t sw t hw t sa t ha read nop read t sd t hd (4) (2) (1) (1) t sw t hw write (5) ce 0 clk ce 1 t sc t hc t ch2 t cl2 t cyc2 r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 5654 drw 12 data out qn qn + 4 oe t cklz (1) t cd2 t ohz (1) t cd2 t sd t hd read write read t sw t hw t sa t ha (4) (2) t sw t hw ce 0 clk ce 1 t ch2 t cl2 t cyc2 t sc t hc
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 12 preliminary %
-=@a%& &*+aa- aa*+ oe 73 ( " " %
-=@a%& &*+aa- aa*+ oe
+" " notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance is determined by the previous cycle control signals. 3. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 5654 drw 13 qn data out t cd1 qn + 1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sw t hw t sa t ha read nop read t cklz (4) (2) (1) (1) t sw t hw write (5) ce 0 clk ce 1 t ch1 t cl1 t cyc1 t sc t hc r/ w address an an +1 t sw t hw an + 2 an + 3 an + 4 an + 5 (4) data in dn + 2 5654 drw 14 qn data out t cd1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sw t hw t sa t ha read write read t cklz (2) dn + 3 t ohz (1) (1) oe t oe ce 0 clk ce 1 t ch1 t cl1 t cyc1 t sc t hc
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 13 preliminary %
-=
+*+@ &4++
4+=
" %
-=@a%& &*+@ &4++
4+=
" notes: 1. ce 0 and oe = v il , ce 1 , r/ w , and cntrst = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5654 drw 15 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5654 drw 16 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 14 preliminary %
-=- @ &4++
4+=
@a%& &
+0 " " %
-=
*
+0 " " notes: 1. ce 0 and r/ w = v il ; ce 1 and cntrst = v ih . 2. ce 0 = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset cycle. 7. cnten = v il advances internal address from ? an ? to ? an +1 ? . the transition shown indicates the time required for the counter to advance. the ? an +1 ? address is written to during this cycle. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 5654 drw 17 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd address an d 0 t ch2 t cl2 t cyc2 q 0 q 1 0 clk data in r/ w cntrst 5654 drw 18 internal (3) address ads cnten t srst t hrst t sd t hd t sw t hw counter reset write address 0 read address 0 read address 1 read address n qn an + 1 an + 2 read address n+1 data out t sa t ha 1 an an + 1 (5) (6) ax (4) (6) .
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 15 preliminary 4

the idt70t9169/59 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asynchronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory appli- cations. ce 0 = v ih or ce 1 = v il for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70t9169/59's for depth expansion configurations. when the pipelined output mode is enabled, two cycles are required to get valid data on the outputs. &
+- +&.6

the idt70t9169/59 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no require- ments for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70t9169/59 can also be used in applications requiring expanded width, as indicated in figure 4. since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 18-bit or wider applications. figure 4. depth and width expansion with idt70t9169/59 5654 drw 19 idt70t9169/59 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 14 /a 13 (1) ce 1 ce 0 v dd v dd idt70t9169/59 idt70t9169/59 idt70t9169/59 control inputs control inputs control inputs control inputs cntrst clk ads cnten r/ w oe note: 1. a 14 is for idt70t9169, a 13 is for idt70t9159.
6.42 idt70t9169/59l high-speed 2.5v 16/8k x 9 synchronous pipelined dual-port static ram industrial and commercial temperature rang es 16 preliminary 0+
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; 2 07/08/02: initial public release corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-611 6 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. note: 1. contact your local sales office for industrial temp range for other speeds, packages and powers. a power 99 speed a package a process/ temperature range blank i (1) commercial (0 cto+70 c) industrial (-40 cto+85 c) 100-pin tqfp (pn100-1) 100-pin fpbga (bf100) speed in nanoseconds 5654 drw 20 l low power 70t9169 70t9159 72k (8k x 9-bit) 2.5v synchronous dual-port ram 144k (16k x 9-bit) 2.5v synchronous dual-port ram commercial & industrial commercial only .. commercial only pf bf 7 9 12 xxxxx device type idt

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